1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device having a burst write mode.
2. Description of the Related Art
In recent years, the performance of parts of computers and other information processing systems has greatly improved. Thus, for semiconductor memory device such as SDRAM (Synchronous Dynamic Random Access Memory), for example, a higher operating speed and an improved data transfer rate, including a multi-bit input/output configuration, are sought.
Specifically, a double data rate (DDR) has come to be employed as a means for increasing the operating speed, in which the clock frequency is increased or data are input or output at both the leading edge and the trailing edge of the clock without increasing the clock frequency.
With the increase in transfer rate, the operation requirement in the circuits cannot be met by writing or reading the data bit by bit. Burst processing (burst read and burst write) for collectively processing several bits of serially input data is required.
At the time of write operation for burst processing (burst write mode), the actual write operation into the core is required to be held before all the data are ready (until the write data for the burst length is prepared). A higher speed of the processing in burst write mode is desired.
The related art and the problem points thereof will be described in detail with reference to the accompanying drawings.